The present invention relates to a semiconductor device having a resistance element.
Multiple resistance elements may be formed in a semiconductor device in some cases. The technology described in Patent Literature 1 for example is a technology that relates to a semiconductor memory device having multiple variable resistance elements. More specifically, that is a technology of forming a dummy element in a memory region where plural variable resistance elements are formed. It describes that thereby the characteristic variation of the variable resistance elements can be reduced.
Then the technology described in Patent Literature 2 for example is a technology that relates to a semiconductor device having a polyresistance formed over an element isolation film over a semiconductor substrate. More specifically, it describes that the dishing phenomenon occurring in an element isolation film can be inhibited by forming an active region at a position close to a resistance element. The dishing phenomenon is a phenomenon of forming a recess in the center of an element isolation film when the element isolation film is flattened by a CMP (Chemical Mechanical Polishing) method.    [Patent Literature 1]    Japanese Unexamined Patent Application Publication No. 2010-219098    [Patent Literature 2]    Japanese Unexamined Patent Application Publication No. 2002-261244